WIP: Add Elementwise Functions support #1500
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Thanks, @SpiritSeeker!
Please, review comments.
| @property | ||
| def cpp_op(self): | ||
| odt_hls_name = self.out_dtype.get_hls_datatype_str() | ||
| return "({0} > 0 ? (%s){0} : (%s)0)" % (odt_hls_name, odt_hls_name) |
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The reversed comparison {0} < 0 is easier for most datatypes.
| inp_bw = self.inp_dtype.bitwidth() | ||
| # The output would be unsigned with same bit-width as input | ||
| # if input was unsigned, else one bit less | ||
| out_bw = inp_bw - 1 if self.inp_dtype.signed() else inp_bw |
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- Consider issuing a warning when constructing a
ElementwiseReLUnode with an unsigned input type. - You can only safely strip a bit from the output datatype if the input datatype is narrow, i.e. within
[-2^(n-1) + 1 : 2^(n-1) - 1].
| odt_hls_name = self.out_dtype.get_hls_datatype_str() | ||
| # Explicitly use the overloads, using hls::exp results in minor errors | ||
| if self.out_dtype.get_canonical_name() == "FLOAT32": | ||
| return "(hls::expf((%s){0}))" % (odt_hls_name) |
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return "hls::exp(%s({0}))" % (odt_hls_name) should be the only return statement. Rely on function overload selection by the argument type for specialization.
| odt_hls_name = self.out_dtype.get_hls_datatype_str() | ||
| # Explicitly use the overloads, using hls::erf results in minor errors | ||
| if self.out_dtype.get_canonical_name() == "FLOAT32": | ||
| return "(hls::erff((%s){0}))" % (odt_hls_name) |
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return "hls::erf(%s({0}))" % (odt_hls_name) should be the only return statement. Rely on function overload selection by the argument type for specialization.
| # Generates C++ code for declaring all streams involved in C++ simulation | ||
| # for testing | ||
| def strm_decl(self): | ||
| # Allways add the output stream to the declarations |
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Why not concise?:
self.code_gen_dict["$STREAMDECLARATIONS$"] = [
# Note: Assumes stream type aliases to be set in defines
"OutStream out0_V;",
"InpStream in0_V;"
]
| #pragma HLS BIND_STORAGE variable=out type=RAM_S2P impl=LUTRAM | ||
| """, | ||
| # Perfect loop nest over all folded output dimensions | ||
| *[for_loop(dim, size) + " {" for dim, size in enumerate(out_shape)], |
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This seems to be equivalent to a single flat loop using the product over all dimensions as its bound.
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| # Add HLS interface directives specifying how to create RTL ports for | ||
| # the top-level function arguments | ||
| self.code_gen_dict["$PRAGMAS$"] += [ |
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Fuse into a single compact append for both lines of code.
| def get_verilog_top_module_intf_names(self): | ||
| # Start collecting interface names in a dictionary starting with clock | ||
| # and reset | ||
| intf_names = {"clk": ["ap_clk"], "rst": ["ap_rst_n"]} |
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Pick up all the other associations as part of the initialization.
3 participants
This PR adds support for elementwise functions (elementwise unary operations), allowing for easy extension to all hls math functions from HLS Math Library. The current PR adds support for ReLU, elementwise Exp, and elementwise Erf functions.
Status of tests:
✔️ ReLU - FLOAT32, FLOAT16, INT, FIXED (cppsim and rtlsim)
✔️ Exp and Erf - cppsim + FLOAT32
✔️ Exp - rtlsim: FLOAT32 and FLOAT16
✖️ Exp and Erf - cppsim + FLOAT16 (numpy and simulated results differ significantly)
✖️ Erf - rtlsim: FLOAT32 and FLOAT16 (RTL watchdog timeout error)